Lesson 011 - PLL Theory by N8MX Andy Meng (Child Prodigy)
Subject: MP20 PLL Lesson #011 - Operating Principles
A little background:
In the old days, (pre-IC) there were a variety of ways devised to obtain stable, yet variable frequencies. Elaborate temperature compensated mechanical hi-Q cavity oscillators were used but these tended to be large and expensive.
Then there was the brute force method used by many which had a separate crystal for each desired frequency. A large rotary switch would make the selection. This also was large and expensive. Not too surprisingly, the concept of how a single crystal could be made to impart it's frequency stability to a wide range LC oscillator had been figured out, but only well funded projects that had to have the performance it offered were able to afford the many programmable counters it required to make.
It all changed about 1976 when the first large scale IC parts containing the counters became available. Many chips now have all the circuits except for some larger C's and R's that need to be picked by the designer.
This method involves selecting a single, fixed (reference) frequency that two separate oscillators will produce an output at. One of the oscillators is a very stable crystal circuit. The other is a VCO that has some tuning range. The VCO almost always runs at the desired output frequency.
Here is where the dividers come into play. The xtal osc gets divided down until it's output is at the ref freq. Using another divider, which is almost always set to a different divide ratio than that of the ref osc, we get an output (from the divider) at the reference frequency....well, almost. Problem is, the VCO drifts around pretty badly. What if we compared both supposedly identical osc outputs and got an error signal voltage that was proportional to the frequency offset? Then if we got the error signal polarity right, we could feed it to the VCO so that if the VCO was too low, the error signal would tend make the VCO speed up. Only when the two were matched, would the error signal be zero. IF we could do this, whenever we changed the divide ratio of the VCO counter, the error signal would cause the VCO to seek out a new frequency to force the error signal to be 0.
The good news is that we can! This is how the MP PLL circuit works. A Phase-Locked Loop (PLL) is a type of frequency synthesizer. A PLL is a feedback loop that controls frequency. The PLL chip itself, a Motorola MC145151 in our case, consolidates many circuits into one device. For more information on this device, check out:
http://www.fpqrp.com/pigg20/SPECS/145151.htm
First of all, a reference oscillator signal is fed into the chip (OSCin, pin 27). This goes through a programmable divider that is called the "R" divider and is set by RA0 - RA2. The division ratio of the reference oscillator input is selectable between eight different values. In our case, pins RA0 and RA2 are left floating, while RA1 is grounded. Since the chip has internal pull-up resistors, the ungrounded pins are high. This sets the internal divider to a division ratio of 2048:1 (the table of values can be found at the above link). Since the reference oscillator runs at approximately 8.192MHz, the internal reference frequency is 4KHz.
The other frequency input is Fin, pin 1. This signal also goes to a programmable divider. This divider is the "N" divider and is set with N0-N13. This divider is the one that changes during operation of the radio, and it sets the frequency in 4KHz (OSCin / "R" ratio) steps. The way that this is accomplished is by dividing the Fin input by "N." Fin will always equal the internal (divided) reference frequency * N. Another way of saying this is R = Fin / N. For instance if the N "port" is set to 00110110111100 binary (3516 decimal), the frequency of the PLL will be: 4KHz = Fin /3516. Re-arranging this, it is: 4KHz * 3516 = Fin. By performing the calculation, we can see that the frequency at Fin would equal 14.066MHz.
The PLL locks the phase of the divided Fin to the phase of the internal reference frequency. This is achieved by sending a feedback output (PDout) to the VCO so that the signals stay locked. To maintain the phase lock, a phase detector is used. The output is DC, and is dependent on the phase difference of the two signals. This controls the error amplifier and loop filter. The loop filter provides a low pass filter function and is an important part of the circuit. It determines the some important aspects of the overall circuit, such lock time, loop stability, and loop bandwidth.
Lock time refers to the time required for the PLL to lock the phase of the two signals during a frequency change. While this is not a major factor in the MP20 due to the naturally slow analog control, in radios such as scanners in which a very short lock time is necessary, lock time is of greater concern.
Loop stability is important because when the divide ratio is changed to change frequency, you want the frequency to smoothly shift from where it is, to where you want it to go, without any ringing. Think of a car that hits a step change in the pavement. Greatest vehicle control exists when the shock absorber does it's job and keeps the car from bouncing up and down after hitting the new road level. Same way in a loop circuit. A properly designed loop filter allows for a quick frequency change without overshoot.
As you can see, there are many factors that go into a careful PLL design. An excellent paper was written by Russ Brown from the Wiltron Company called "Phase Lock Loop Fundamentals" which describes in words many of the aspects of a PLL. It actually goes into the subject reasonably deep, using diagrams and providing design equations. Let me know of you are interested in this...
That's All! Thanks for being patient with the long delay time on this lesson. If you have any questions, just ask.
Thanks to my dad for helping me write this, especially the history part...
72/73, es oo,
Andy Meng N8MX